Reliability Tradeoffs in Design of Cache Memories

Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient read/write access to memory, and their reliability is essential to assure dependable computing. Errors that occur in the cache can corrupt data values or result in invalid state, and can easily propagate throughout the system to cause data integrity issues. One of the main threats to cache reliability is soft errors (i.e., transient errors). These errors, which can occur more often than hard (permanent) errors, arise from Single Event Upsets (SEU) caused by energetic-particle strikes such as neutrons and alpha particles. Researchers have shown that in current systems, memory elements are the most vulnerable system component to soft errors. In this paper, we examine the vulnerability (on a per bit basis) of different components of on-chip L2 caches, including data and tag bits. Vulnerability per bit is important when considering the reliability of a design; the higher the per-bit vulnerability of a structure, the greater its impact on overall reliability. We show that the vulnerability per bit of the tag array and data array differ significantly, and thus should motivate our implementation decisions when considering design tradeoffs for reliability.