International audienceWith the progress of the technology, the presence of transient faults (e.g. bit-flipping errors) in cache memories becomes a challenge, especially in embedded real-time systems. These are mission critical systems that are often subject to both fault-tolerant and real-time constraints.To reduce the impact of transient faults, hardware protection mechanisms are usually proposed. However, these mechanisms introduce too much pessimism in the computation of the worst-case execution time of a task, decreasing the overall system performance.In this paper, we propose a methodology to evaluate and reduce the vulnerability of hard real-time applications to soft errors in IL1 cache memories.We use static analysis tools to analyze...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Continuous technology scaling has brought us to a point, where transistors have become extremely sus...
Soft errors (also called transient errors, or single event upsets) are one of the vital errors that ...
Safety critical real-time applications in aviation, automotive and industrial automation have to gua...
Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM a...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
Cache memories have been extensively used to bridge the gap between high speed processors and relati...
Modern processors with an extensive cache structure are considered not to be useful in real-time sys...
Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making...
While the cache memory designed into advanced processors can significantly speed up the average perf...
Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM a...
Information integrity in cache memories is a fundamental requirement for dependable computing. Conve...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Continuous technology scaling has brought us to a point, where transistors have become extremely sus...
Soft errors (also called transient errors, or single event upsets) are one of the vital errors that ...
Safety critical real-time applications in aviation, automotive and industrial automation have to gua...
Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM a...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
Cache memories have been extensively used to bridge the gap between high speed processors and relati...
Modern processors with an extensive cache structure are considered not to be useful in real-time sys...
Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making...
While the cache memory designed into advanced processors can significantly speed up the average perf...
Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM a...
Information integrity in cache memories is a fundamental requirement for dependable computing. Conve...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...