Reliability tradeoffs in design of cache memories

Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient read/write access to memory, and their reliability is es-sential to assure dependable computing. Among the pri-mary threats to cache reliability are soft (transient) er-rors. When incident in a cache, these errors can cor-rupt data values or result in invalid state, and can easily propagate throughout the system to cause data integrity issues. In most modern processors, a significant portion of the chip area is dedicated to the L2 cache. In this paper, we examine the vulnerability (on a per bit basis) of different components of on-chip L2 caches, including data and tag bits. Vulnerability per bit is important when considering the reliability of a design; the higher the per-bit vulnera-bility of a structure, the greater its impact on overall re-liability. We show that the vulnerability per bit of the tag array and data array differ significantly, and thus should motivate our implementation decisions when considering design tradeoffs for reliability.