Models for soft errors in low-level caches

2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is critical to evaluate the relative merits of various soft-error protection schemes available. Since protection has implications for power, energy and performance, it is desirable to avoid over provisioning. The semiconductor industry expects that one single event upset (SEU) will cause spatial multi-bit upsets (MBUs) more frequently in the near future so that, by the year 2016, all SEUs will likely to be spatial MBUs rather than single bit upsets (SBUs). This new trend contradicts what has been assumed until now for modeling, benchmarking and evaluating the soft-error reliability of memory structures. No existing framework can evaluate the realistic impact of multiple SBUs as well as spatial MBUs on memory structures. ❧ In this dissertation, we develop novel soft-error reliability benchmarking models and frameworks that address the complex scenarios produced collectively by SBUs and MBUs, in the context of large, low-level caches. First, we introduce a reliability benchmarking framework called PARMA (precise analytical reliability model for architecture). PARMA is a rigorous analytical framework that accurately accounts for multiple SBUs over time to measure the failure rate under any protection scheme. Second, we develop a reliability evaluation framework called MACAU (a Markov model for reliability evaluations of caches under single-bit and multi-bit upsets). MACAU addresses the overlapping effects of SBUs and spatial MBUs over time, to benchmark caches protected by various codes. Additionally MACAU is general enough to compute the intrinsic MTTFs (mean time to failure) of scrubbed caches. Finally, a novel reliability-aware sampling method to accelerate model-based reliability simulations is introduced and evaluated. This sampling technique solves the significant simulation slowdown that all model-based reliability benchmarking frameworks, including PARMA, MACAU, and AVF (Architectural Vulnerability Factor) analysis suffer from. The sampling accuracy is guaranteed by statistically controlling the FIT (Failures-In-Time) estimation error using a profiling technique. The PARMA or MACAU frameworks integrated with the reliability-aware sampling method are unique and invaluable tools for designers to evaluate and design reliable chips efficiently