Evaluating Cache Vulnerability to Transient Errors for The Uni-processor and Multi-processor Systems

Soft errors (also called transient errors, or single event upsets) are one of the vital errors that causes irrelevant programming/functional out-put, impacting the reliability of any electronic system. This thesis addresses how the soft error occurrence is impacting the Micro-processor cache reliability which in turn affecting the reliability of the entire processor, using a methodology called Cache Vulnerability Factor (CVF). The CVF indicates the probability that soft errors of caches can impact other components. In this research we evaluate the degree of reliability for variety of cache memories, including the L1 I-cache, the write-through L1 D-cache, and the L2 cache for both Uni-processor and Multi-processor systems. For this, we made use of SESC (Event-driven simulator) and SPEC 2k benchmarks as applications for simulation. Our experimental results are based up on the Symmetrical Multiprocessing (SMP) configuration option available in SESC simulator for both the Uni-processor & multi-processor systems