Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures

Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. Reconfiguring the logic is still an expensive operation and precludes frequent configuration changes. To reduce the overheads involved in reconfiguration, devices with configuration caches and multiple contexts are being designed. Reconfigurable computing solutions are typically designed by composing lower level modules or library components. Each operation in an application can be implemented by using any one among several of these modules or hardware objects. This gives rise to the problem of choosing an optimal set of modules for utilizing the cache or the multiple contexts. This paper develops a formal methodology for selection of these modules to minimize the total execution time. The total execution time includes the reconfiguration time and the computation time in various configurations. We focus on loop computations since they are the most compute int..