A hierarchical architectural framework for reconfigurable logic computing

Recently there has been growing interest in using Reconfigurable Logic (RL) for computation because of the significant performance gains that they can provide over traditional architectures on many classes of workloads. While there is a rich body of prior work proposing a variety of reconfigurable systems, we believe there hasn't been an attempt to clearly identify the architectural tradeoff spaces for an RL compute engine and to clearly separate architectural choices from implementation ones. In this paper, we propose a taxonomy of architectural choices for RL computing. The taxonomy covers a multi-dimensional tradeoff space involving choices on operations, data types, states, sequencing, and communication primitives, and provides architects with a systematic framework for making decisions on these choices. We highlight the implementation and programmability consequences of such decisions, and wherever appropriate, punctuate the descriptions with examples of prior work that have made specific choices. Finally, we demonstrate how our proposed taxonomy is general enough to be hierarchically composed into a multi-level framework capturing the architectural design space of complex systems based on RL, such as heterogeneous systems comprising of traditional CPUs augmented with RL engines. ? 2013 IEEE.EI