Design space exploration for dynamically reconfigurable architectures

By incorporating reconfigurable hardware in em-bedded system architectures it has become easier to satisfy the performance constraints of demanding appli-cations while lowering system cost. In order to evalu-ate the performance of a candidate architecture, the nodes (tasks) of the data flow graphs that describe an appli-cation must be assigned to the computing resources of the architecture: programmable processors and reconfig-urable FPGAs, whose run-time reconfiguration capabilities must be exploited. In this paper we present a novel de-sign exploration tool—based on a local search algorithm with global convergence properties—which simultane-ously explores choices for computing resources, assign-ments of nodes to these resources, task schedules on the programmable processors and context definitions for the re-configurable circuits. The tool finds a solution that min-imizes system cost while meeting the performance con-straints; more precisely it lets the designer select the quality of the optimization (hence its computing time) and finds ac-cordingly a solution with close-to-minimal cost. 1