Cache Architectures for Reconfigurable Hardware

Abstract—The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguration operations at the lower reconfiguration level. Whereas the upper reconfiguration level is used to configure the capabilities that are actually available for the lower level. The actual state of each reconfiguration level is determined by a corresponding context. The use of context caches and strategies for their use in ordinary 1-level reconfigurable architectures have been studied several times in the literature. Here we propose different architectures for caches which can store lower and upper level contexts for 2-level reconfigurable hardware. In addition we propose several heuristics that reduce the total reconfiguration costs when using upper level cache. Experimental results for fine grained and coarse grained two-level reconfigurable architectures are presented. It is also shown that the optimal use of an upper level cache is an NP-hard problem. Keywords—run-time reconfiguration, multi-level reconfiguration, cache I