Configuration caching and swapping

Abstract. Speedups of coupled processor-FPGA systems over tradi-tional microprocessor systems are limited by the cost of hardware recon-figuration. In this paper we compare several new configuration caching algorithms that reduce the latency of reconfiguration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the configurations is reduced, low-ering the configurable overhead.