Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems

. Configurable Arithmetic Logic Units (ALUs) offer opportunities for adapting the underlying hardware to the computation for efficiency. The problem of identifying the optimal configurations at different steps in a program is a very complex issue but allows the power of these ALUs to be maximally used if solved. This paper focuses on developing an automatic compilation framework for exploiting operator parallelism within loop nests. The focus of this analysis is on identifying and maximally using configurations to avoid costly reconfiguration overheads. In our framework, initially some operator and loop transformations are carried out to expose more opportunities for configuration reuse. We then present a two pass solution. The first pass attempts to group the statements that have `similar' configuration demands together into cutsets and generates the corresponding configurations. The second pass analyzes the trade-offs between costs and benefits of reconfigurations across different c..