Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices

Abstract. State-of-the-art behavioral synthesis tools for reconfigurable architectures barely have high-level transformations in order to achieve highly parallelized implementations. If any, they apply loop unrolling to obtain a higher throughput. In this paper, we use the PARO behavioral synthesis tool which has the unique ability to perform both loop unrolling or loop partitioning. Loop unrolling replicates the loop kernel and exposes the parallelism for hardware implementation. Whereas, partitioning tiles the loop program onto a regular array consisting of tightly coupled processing elements. The usage of the same design tool for both the variants enables for the first time, a quantitative evaluation of the two approaches with help of selected computationally intensive algorithms. The processor array approach achieves in all experiments a far better throughput, up to 61% more compared with loop unrolling because of its regularity and the clustering of resources into several processing elements