Using Estimates from Behavioral Synthesis Tools

This paper considers the role of performance and area esti-mates from behavioral synthesis in design space exploration. We have developed a compilation system that automati-cally maps high-level algorithms written in C to application-specific designs for Field Programmable Gate Arrays (FP-GAs), through a collaboration between parallelizing com-piler technology and high-level synthesis tools. Using several code transformations, the compiler optimizes a design to in-crease parallelism and utilization of external memory band-width, and selects the best design among a set of candidates. Performance and area estimates from behavioral synthesis provide feedback to the compiler to guide this selection. Es-timates can be derived far more quickly (up to several orders of magnitude faster) than full synthesis and place-and-route, thus allowing the compiler to consider many more designs than would otherwise be practical. In this paper, we exam-ine the accuracy of the estimates from behavioral synthesis as compared to the fully synthesized designs for a collection of 209 designs for five multimedia kernels. Though the es-timates are not completely accurate, our results show that the same design would be selected by the design space explo-ration algorithm, whether we use estimates or actual results from place-and-route, because it favors smaller designs and only increases complexity when the benefit is significant