Programmable Chip based on hardware-software

Abstract—T In this paper, we propose an approach based on hardware-software partitioning to minimize logic area of a SOPC circuit "System on a Programmable Chip". This approach minimizes the SOPC area while satisfying a time constraint. To minimize this area, we propose an algorithm to determine the critical path with the largest number of hardware tasks in a given data flow graph. Once these hardware tasks are determined, they will be implemented on the software. In this way we minimize the number of tasks used by the HW and increase the number of tasks used by the SW, where we have a minimization of the area. Index Terms — Logic area, hardware-software partitioning algorithm, temporal constraint, SOPC. I