A Hardware/Software Partitioning Algorithm for Pipelined Instruction Set

Abstract — This paper introduces a new HW/SW par-titioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Spe-cific Integrated Processor). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and soft-ware so that the HW cost (gate count) of the designed pipelined ASIP is minimized under given execution cy-cle and power consumption constraints. A branch-and-bound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system. The experimental results show that the proposed method is found to be effective and efficient.