Design and Implementation of a Pipelined Instruction Decoder for an ASIP DSP

AbstractAn Application Specific Instruction set Processor (ASIP), a component used in System-on-a-Chip (SoC) consists of an Instruction Set Architecture called ISA designed according to the application which will be running on the processor. This specialization of the core provides a trade-off between the flexibility of a general purpose CPU and the performance of Application Specific Integrated Circuits (ASIC). During the execution of instructions in such a processor, instruction decoding is a major task for identifying instructions and generating control signals for data-paths .In this paper, a novel Instruction decoding technique is proposed that employs pipelining along with Separated Instruction Decoding(SID) and Decoder Structure Optimization (DSO) techniques to decrease the area and power. The proposed design is implemented using Verilog HDL in Xilinx and optimization results are obtained using Cadence RC Compiler 130nm technology. The experimental results shows that there is 32% improvement in area and a 58% improvement in power compared with the conventional decoder technique. The proposed pipelining logic improves the clock period compared with the existing Instruction Decoding Unit (IDU) technique with an improved area and power performance thereby making the proposed IDU technique more efficient