A Hardware/Software Partitioning Algorithm for Pipelined Instruction Set Processor

Abstract This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this paper is to nd a set of HW implemented operations to achieve the highest performance o f a p i p elined ASIP under a given gate count and power consumption constraint. The method enables to estimate the performance and pipeline hazards of the designed ASIP very accurately. The experimental results show that the proposed method i s eective and quite ecient