The Kernighan/Lin heuristic, also known as min-cut, has been extended very successfully for circuit partitioning over several decades. Those extensions customized the heuristic and its associated data structure to rapidly compute the minimum-cut metric required during circuit partitioning; thus, those extensions are not applicable to problems requiring other metrics. In this paper, we extend the heuristic for functional partitioning in a manner applicable to the codesign problem of hardware/software partitioning as well as to hardware/hardware partitioning. The extension customizes the heuristic and data structure to rapidly compute execution-time and communication metrics, crucial to hardware and software partitioning, and leads to nearlin...
The problem of hardware-software partitioning for systems that are being designed as multifunction s...
Abstract: Hardware Software partitioning of a task graph refers to the mapping of task nodes to phys...
Hardware/software (HW/SW) partitioning is one of the key challenges in HW/SW codesign. This paper pr...
The Kernighan/Lin graph partitioning heuristic, also known as min-cut or group migration, has been e...
The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is n...
Partitioning a system's functionality among interacting hardware and software components is an impor...
In system-level design, applications are represented as task graphs where tasks (called nodes) have ...
Hardware/software (HW/SW) partitioning is one of the crucial steps of co-design systems. It determin...
Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied...
We demonstrate circuits that generate set and integer partitions on a set S of n objects at a rate o...
Logic replication is known to be an effective technique to reduce the number of cut nets in partitio...
[[abstract]]Logic replication is known to be an effective technique to reduce the number of cut nets...
[[abstract]]Logic replication is known to be an effective technique to reduce the number of cut nets...
[[abstract]]Circuit partitioning is one of the central problems in VLSI system design. The primary o...
[[abstract]]Logic replication is known to be an effective technique to reduce the number of cut nets...
The problem of hardware-software partitioning for systems that are being designed as multifunction s...
Abstract: Hardware Software partitioning of a task graph refers to the mapping of task nodes to phys...
Hardware/software (HW/SW) partitioning is one of the key challenges in HW/SW codesign. This paper pr...
The Kernighan/Lin graph partitioning heuristic, also known as min-cut or group migration, has been e...
The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is n...
Partitioning a system's functionality among interacting hardware and software components is an impor...
In system-level design, applications are represented as task graphs where tasks (called nodes) have ...
Hardware/software (HW/SW) partitioning is one of the crucial steps of co-design systems. It determin...
Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied...
We demonstrate circuits that generate set and integer partitions on a set S of n objects at a rate o...
Logic replication is known to be an effective technique to reduce the number of cut nets in partitio...
[[abstract]]Logic replication is known to be an effective technique to reduce the number of cut nets...
[[abstract]]Logic replication is known to be an effective technique to reduce the number of cut nets...
[[abstract]]Circuit partitioning is one of the central problems in VLSI system design. The primary o...
[[abstract]]Logic replication is known to be an effective technique to reduce the number of cut nets...
The problem of hardware-software partitioning for systems that are being designed as multifunction s...
Abstract: Hardware Software partitioning of a task graph refers to the mapping of task nodes to phys...
Hardware/software (HW/SW) partitioning is one of the key challenges in HW/SW codesign. This paper pr...