Add to ORKGThis paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-testability while generating control sequences for justification and propagation at register-transfer level. Since the method fully utilizes functions of controllers as well as datapaths, it achieves small area overhead.http://library.naist.jp/mylimedio/dllimedio/show.cgi?bookid=100037129&oldid=6790
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is...
We consider the problem of designing self-checking controllers for controller / datapath architectur...
Most behavioral synthesis and design for testability techniques target subsequent gate-level sequent...
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL)....
In the paper, it is shown how testability analysis can be used both to modify digital data path for ...
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
This paper presents a method for deriving a BIST specification from the initial specification of dat...
Area and test time are two major overheads encountered during data path synthesis for BIST. This pap...
This paper presents an attempt towards design quality improvement by incorporating of self-testabili...
In this paper, we present a method for analyzing the testability of a circuit during high level synt...
International audienceWe present a behavioral synthesis method aimed at generating testabledatapaths...
We consider the problem of designing self-checking controllers for applications with sequential data...
Abstract. The paper presents the original algorithms for generation of sequences of microinstruction...
This paper presents a testability analysis and improvement technique for the controller of an RT lev...
In the paper the process of the test controller design and synthesis on register transfer level is d...
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is...
We consider the problem of designing self-checking controllers for controller / datapath architectur...
Most behavioral synthesis and design for testability techniques target subsequent gate-level sequent...
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL)....
In the paper, it is shown how testability analysis can be used both to modify digital data path for ...
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
This paper presents a method for deriving a BIST specification from the initial specification of dat...
Area and test time are two major overheads encountered during data path synthesis for BIST. This pap...
This paper presents an attempt towards design quality improvement by incorporating of self-testabili...
In this paper, we present a method for analyzing the testability of a circuit during high level synt...
International audienceWe present a behavioral synthesis method aimed at generating testabledatapaths...
We consider the problem of designing self-checking controllers for applications with sequential data...
Abstract. The paper presents the original algorithms for generation of sequences of microinstruction...
This paper presents a testability analysis and improvement technique for the controller of an RT lev...
In the paper the process of the test controller design and synthesis on register transfer level is d...
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is...
We consider the problem of designing self-checking controllers for controller / datapath architectur...
Most behavioral synthesis and design for testability techniques target subsequent gate-level sequent...