In this paper, we introduce strong self-testability for data paths at register transfer level (RTL). A high-level synthesis scheme is proposed for producing such strongly self-testable data paths. This is achieved by incorporating testability constraints during processes of register assignment and interconnection assignment. This method is based on the use of test resources reusability to improve the self-testability of data path. Experimental results are presented to demonstrate the effectiveness of the proposed approach.EI
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate e...
A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. At...
There have been several recent attempts to include duplication-based on-line testability in behaviou...
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL)....
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
This paper presents an attempt towards design quality improvement by incorporating of self-testabili...
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-te...
BIST techniques have evolved as cost-effective techniques for digital VLSI testing. A prime concern ...
In this paper, we present a method for analyzing the testability of a circuit during high level synt...
Most behavioral synthesis and design for testability techniques target subsequent gate-level sequent...
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The metho...
Area and test time are two major overheads encountered during data path synthesis for BIST. This pap...
Area and test time are two major overheads encountered during data path high level synthesis for BIS...
Recent research for testable designs has focussed on inserting test structures by re-arranging an Re...
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate e...
A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. At...
There have been several recent attempts to include duplication-based on-line testability in behaviou...
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL)....
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
This paper presents an attempt towards design quality improvement by incorporating of self-testabili...
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-te...
BIST techniques have evolved as cost-effective techniques for digital VLSI testing. A prime concern ...
In this paper, we present a method for analyzing the testability of a circuit during high level synt...
Most behavioral synthesis and design for testability techniques target subsequent gate-level sequent...
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The metho...
Area and test time are two major overheads encountered during data path synthesis for BIST. This pap...
Area and test time are two major overheads encountered during data path high level synthesis for BIS...
Recent research for testable designs has focussed on inserting test structures by re-arranging an Re...
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate e...
A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. At...
There have been several recent attempts to include duplication-based on-line testability in behaviou...
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