Guided Hardware Sharing procedure for Improving Testability

This paper presents a method to carry out the register allocation/binding phase of a High Level Synthesis flow with testability considerations. Testability problems are identified at behavioral level and are eliminated as much as possible during this phase turning testability/area trade-off to account. Proposed method is based on high level normalized testability measures, it allows to improve the testability of datapath-like structures without requiring any lower level DFT techniques. Keywords: Synthesis For Testability 1. Introduction Testability improvement of a datapath can be tackled at various levels of description. At Register Transfer Level (RTL) as at gate level, the structure needs to be modified using DFT techniques as scan, test point insertion, .... The overhead they involve is difficult to manage in the design flow since they intervene once the structure is already fixed by the synthesis steps. As a counterpart, high level synthesis allows to explore the solution space..