Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto the rDPA without manual interaction. The required algorithms of this synthesis system are described in detail. Optimization techniques like loop folding or loop unrolling are sketched. The rDPA is scalable to arbitrarily large arrays and reconfigurable to be adaptable to the computational problem. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The rDPA can be used as a reconfigurable ALU for bus oriented systems as well as for rapid prototyping of high speed datapaths. I
This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-te...
The University of Texas at El Paso has collaborated with the University of New Mexico Microelectroni...
As datapath chips such as microprocessors and digital signal processors become more complex, efficie...
From high level synthesis point of view, target design can be divided into two parts: controller and...
Datapath optimisation has a great impact on the efficiency of computationally intensive embedded des...
COBRA is a behavioral high level synthesis tool for datapath dominated applications. It uses a regul...
grantor: University of TorontoIn digital signal processing (DSP) ICs and microprocessors, ...
MAHA is a program which implements an algorithm for register level synthesis of data paths from a da...
We present a robust datapath allocation method that is flexible enough to handle constraints imposed...
Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, ty...
Reconfigurable systems have been shown to achieve significant performance speedup through architectu...
This thesis presents the design of a reconfigurable datapath suitable for use in constructing a reco...
Abstract—A shared bus is a suitable structure for minimizing the interconnections costs in system sy...
International audienceThis paper presents a High Level Synthesis (HLS) method for specialized coproc...
In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistica...
This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-te...
The University of Texas at El Paso has collaborated with the University of New Mexico Microelectroni...
As datapath chips such as microprocessors and digital signal processors become more complex, efficie...
From high level synthesis point of view, target design can be divided into two parts: controller and...
Datapath optimisation has a great impact on the efficiency of computationally intensive embedded des...
COBRA is a behavioral high level synthesis tool for datapath dominated applications. It uses a regul...
grantor: University of TorontoIn digital signal processing (DSP) ICs and microprocessors, ...
MAHA is a program which implements an algorithm for register level synthesis of data paths from a da...
We present a robust datapath allocation method that is flexible enough to handle constraints imposed...
Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, ty...
Reconfigurable systems have been shown to achieve significant performance speedup through architectu...
This thesis presents the design of a reconfigurable datapath suitable for use in constructing a reco...
Abstract—A shared bus is a suitable structure for minimizing the interconnections costs in system sy...
International audienceThis paper presents a High Level Synthesis (HLS) method for specialized coproc...
In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistica...
This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-te...
The University of Texas at El Paso has collaborated with the University of New Mexico Microelectroni...
As datapath chips such as microprocessors and digital signal processors become more complex, efficie...