An FPGA based FIFO with efficient memory management

In this paper, an FPGA based FIFO with efficient memory management is proposed, which allows fast forwarding of real-time Ethernet frames. There are two main drawbacks of the existing FIFO implementations with respect to the buffering of Ethernet frames. Currentness of data is not guaranteed in case of buffer overflow because the new frames are dropped in this case. Furthermore, exhaustive resources are required for traffic priorization because an individual FIFO is required for each priority level. The proposed FIFO incorporates efficient strategies for both frame dropping and traffic priorization. The approach is based on a small ring buffer for meta data of individual frames and a page table that maps the frames to pages in RAM where the data bits of the frame are stored. The FIFO has been implemented on a low-cost Xilinx Spartan 6 FPGA. The solution requires little overhead for page table and ring buffer. Compared to an implementation with standard FIFOs that incorporates traffic priorization and frame dropping, RAM size is decreased from 44 kbytes to 2.7 kbytes