A content addressable FIFO for shared memory ATM switch architectures

grantor: University of TorontoA Content Addressable FIFO (CAFIFO) is a scalable address queuing structure for shared buffer ATM switches. Unlike conventional systems employing address copying, a CAFIFO-based system requires only one storage element per cell address. Logical output queues are managed in one physical structure requiring less queuing memory and write bandwidth. The CAFIFO returns the earliest cell destined for a particular output port by means of a fully parallel associative search. Resulting memory fragmentation is removed by a novel compression algorithm eliminating the need for shifting. A self-timed 16.5Kb (512 entry) test chip (7.2 mm$\sp2)$ was implemented in 0.8 $\mu$m BiCMOS technology for a 16 x 16 switch. Reasonable aspect ratio and floorplan is achieved with a single ported 2-D search and multiple match mechanism with shared match-line. Simulations indicate a performance of 40 MHz or 40 Mcells/second. The CAFIFO concept is extendible to support several priorities with an appropriate CAM architecture and additional tag bits.M.A.Sc