Efficient pcfpga communication over gigabit ethernet

As FPGAs become larger and more powerful, they are in-creasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottle-neck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to a general purpose CPU, there exist several applications with I/O re-quirements for which Gigabit Ethernet is sufficient. To this end, we present the design of an efficient UDP/IP core for PC-FPGA communication that has been designed to occupy a minimum amount of hardware resources on the FPGA. An observation regarding the internet checksum al-gorithm, allows us to reduce the hardware requirements for computing the checksum. Furthermore, this property also allows for initiating packet transmission immediately, i.e., the UDP/IP core can start a transmission without the require-ment of receiving, storing, and processing user data before-hand. The UDP/IP core is available as open-source code. A comparison with related work on UDP/IP core implemen-tations shows that our implementation is significantly more efficient in terms of resource utilization and performance. The experimental results were obtained on a real-world sys-tem and we also make available the PC software test appli-cation that is used for performance assessment to allow for reproduction of our results. 1