Enabling Dynamically Reconfigurable Technologies in Mid Range Computers Through PCI Express

Abstract. Efficient I/O access is crucial in reconfigurable hardware platforms for implementing high-performance systems. Such platforms can outperform CPUs and GPGPUs in executing applications charac-terized by inherent parallelism. However, the system-level performance depends heavily on sustaining high transfer rates for feeding data into the reconfigurable hardware and getting the results back to the end-user. In the present work we propose and implement a hybrid system com-prising a host computer and an FPGA platform. The latter acts as co-processor into which hardware accelerators are loaded and executed in a transparent way, i.e. user is not involved in FPGA programming neither controlling its execution. Depending on the user request, the FPGA can be reconfigured either partially or entirely. Initially, we discuss the cur-rent state-of-the-art on I/O interfaces attached to FPGAs focusing pri-marily on the PCI Express (PCIe). Then, we present our system on which we implemented a design for measuring end-to-end throughput. We have developed a simple yet functional interface for serving the communica-tion between software and hardware over PCIe v1.0 bus. At system-level, we achieved a throughput of 544 MBytes/s and 618 MBytes/s for DMA writes and reads respectively, over a PCIe four-lane (x4) connection. This includes all overhead such as communication delays and systems calls for requesting services from the operating system. Our work can be used as the basis for programming and executing hardware accelerators under the control of a run-time system.