A modern approach to high speed I/O interfacing is proposed through the use of a flexible architecture based upon Field Programmable Gate Arrays (FPGA) and the PCI bus. Three distinct solutions are reviewed, all manufactured according to PMC (PCI Mezzanine Card) standard: one solution is CPU-based and the other two are CPU-less. The reconfigurability of the architectures is emphasized, showing that, by means of modern design techniques, one can easily partition between hardware and software some CPU-demanding or high latency tasks that are typical of modern Data Acquisition Systems
Significant problems have inhibited the wide adoption of reconfigurable computing, including the dif...
Data transfers are handled by the computer bus which connects the device to the memory. The data bus...
Abstract- In order to meet the demand of high-speed digital data processing and achieve high-speed c...
Abstract. Efficient I/O access is crucial in reconfigurable hardware platforms for implementing high...
This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to a...
International audienceThis paper presents a communication-centric reconfigurable design for FPGA Mez...
Summarization: Efficient I/O access is crucial in reconfigurable hardware platforms for implementing...
This thesis investigates the plausibility of designing and developing a versatile, reusable, high sp...
. Reconfigurable hardware provides new architectural possibilities for high performance computing. I...
Abstract- High volume and high throughput rates are the need for high speed data acquisition applica...
Programmable System-on-Chips (SoC) are a flexible solution to offload part of the computational powe...
Field programmable gate arrays are a class of integrated circuit that enable logic functions and int...
The work describes hardware layer of the universal, parameterized communication interfacefor applica...
Tato práce se věnuje přenosu dat mezi PC a FPGA za pomocí PCI Express (PCIe) rozhraní. V teoretické ...
A readout card based on the standard PCI 32-bit/33 MHz bus has been developed for the fast readout o...
Significant problems have inhibited the wide adoption of reconfigurable computing, including the dif...
Data transfers are handled by the computer bus which connects the device to the memory. The data bus...
Abstract- In order to meet the demand of high-speed digital data processing and achieve high-speed c...
Abstract. Efficient I/O access is crucial in reconfigurable hardware platforms for implementing high...
This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to a...
International audienceThis paper presents a communication-centric reconfigurable design for FPGA Mez...
Summarization: Efficient I/O access is crucial in reconfigurable hardware platforms for implementing...
This thesis investigates the plausibility of designing and developing a versatile, reusable, high sp...
. Reconfigurable hardware provides new architectural possibilities for high performance computing. I...
Abstract- High volume and high throughput rates are the need for high speed data acquisition applica...
Programmable System-on-Chips (SoC) are a flexible solution to offload part of the computational powe...
Field programmable gate arrays are a class of integrated circuit that enable logic functions and int...
The work describes hardware layer of the universal, parameterized communication interfacefor applica...
Tato práce se věnuje přenosu dat mezi PC a FPGA za pomocí PCI Express (PCIe) rozhraní. V teoretické ...
A readout card based on the standard PCI 32-bit/33 MHz bus has been developed for the fast readout o...
Significant problems have inhibited the wide adoption of reconfigurable computing, including the dif...
Data transfers are handled by the computer bus which connects the device to the memory. The data bus...
Abstract- In order to meet the demand of high-speed digital data processing and achieve high-speed c...