RTL design techniques of asynchronous FIFO memory blocks with area and power consumption optimizations

this paper presents several new asynchronous FIFO designs. While most existing FIFO’s have higher throughput for higher latency, our goal is to achieve very low latency while maintaining good throughput. The designs are implemented as circular arrays of cells connected to common data buses. Data items are not moved around the array once; they are enqueued. Each cell’s input and output behavior is dictated by the flow of two tokens around the ring: one that allows enqueuing data and one that allows dequeuing data. Since the problems were found in gray code's nature, both FIFO architectures represented in this paper use a modified gray code counters to pointers comparison and addressing the memory array. In the first architecture of FIFO buffer, memory array is addressed by binary code while the pointers are converted to gray codes and compared synchronously. In the second architecture of FIFO buffer memory array is addressed by gray code, but the gray code pointers comparison proceeds asynchronously. These changes give the advantage over the first architecture to reduce latency and power consumption