Expert Verilog, SystemVerilog & Synthesis Training Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons

An interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFO comparison method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #2) is included. This FIFO design paper builds on information already presented in another FIFO design paper where the FIFO pointers are synchronized into the opposite clock domain before running "FIFO full " or "FIFO empty " tests. The reader may benefit from first reviewing the FIFO Style #1 method before proceeding to this FIFO Style #2 method. Post-SNUG Editorial Comment (by Cliff Cummings) Although this paper was voted “Best Paper- 1st Place ” by SNUG attendees, this paper builds off of a second FIF