LOW LATENCY ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) IN DUAL-SUPPLY SYSTEMS

Low latency asynchronous first-in-first-out (FIFO) in dual-supply systems is presented in this paper. A new asynchronous FIFO cell is proposed and can be used to communicate data items among modules not only at different clock frequencies for globally-asynchronous locally-synchronous (GALS) systems but also in dual-supply systems. The properties of the asynchronous FIFO architecture with peripheral handshake circuits in asynchronous wrappers are low latency, low power and scalable. For FIFO size of eight, simulation shows that the latency is 1.38ns at VDDL=0.9V for sender’s module and VDDH=1.5V for receiver’s module and the power dissipation is reduced about 69 % compared to the FIFO cell without level converters. The simulation results are based on the TSMC 0.13um CMOS technology