Hybrid error-detection techniques combine software techniques with an external hardware module that monitors the execution of a microprocessor. The external hardware module typically observes the control flow at the input or at the output of the microprocessor and compares it with the expected one. This paper proposes a new hybrid technique that monitors the control flow at both points and compares them to detect possible errors. The proposed approach does not require any software modification to detect control-flow errors. Fault-injection campaigns have been performed on an LEON3 microprocessor. The results show full control-flow error detection with no performance degradation and small area overhead. A complete solution can be obtained by...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
This paper presents a non-intrusive hybrid fault detection approach that combines hardware and softw...
This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observ...
Hybrid error-detection techniques combine software techniques with an external hardware module that ...
The improvement of dependability in computing systems requires the evaluation of fault tolerance mec...
Shrinking microprocessor feature size and growing transistor density may increase the soft-error rat...
The use of microprocessor-based systems is gaining importance in application domains where safety i...
This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchd...
Today, embedded systems are being used in many (safety-critical) applications. However, due to their...
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Art...
International audienceThis paper presents a non-intrusive hybrid fault detection approach that combi...
Software-based fault tolerance techniques are a low-cost way to protect processors against soft erro...
The use of microprocessor-based systems is gaining importance in application domains where safety is...
This article proposes a software error mitigation approach that uses the single instruction multiple...
This thesis addresses three important steps in the selection of error detection mechanisms for micro...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
This paper presents a non-intrusive hybrid fault detection approach that combines hardware and softw...
This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observ...
Hybrid error-detection techniques combine software techniques with an external hardware module that ...
The improvement of dependability in computing systems requires the evaluation of fault tolerance mec...
Shrinking microprocessor feature size and growing transistor density may increase the soft-error rat...
The use of microprocessor-based systems is gaining importance in application domains where safety i...
This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchd...
Today, embedded systems are being used in many (safety-critical) applications. However, due to their...
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Art...
International audienceThis paper presents a non-intrusive hybrid fault detection approach that combi...
Software-based fault tolerance techniques are a low-cost way to protect processors against soft erro...
The use of microprocessor-based systems is gaining importance in application domains where safety is...
This article proposes a software error mitigation approach that uses the single instruction multiple...
This thesis addresses three important steps in the selection of error detection mechanisms for micro...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
This paper presents a non-intrusive hybrid fault detection approach that combines hardware and softw...
This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observ...