Hybrid Lockstep Technique for Soft Error Mitigation

This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine a software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dualcore ARM microprocessor and validated with low energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross-section of the benchmarks tested, even considering the worst-case scenario.This work has been supported in part by the Spanish Ministry of Science and Innovation under the projects PID2019-106455GB-C22, PID2019-106455GB-C21; and by the Community of Madrid under grant IND2017/TIC-7776