Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, multicore machines are dominating the architectural spectrum today in various application domains. These two trends require a fresh look at resiliency of multithreaded applications against transient errors from a software perspective. In this paper, we propose and evaluate a new metric called the Thread Vulnerability Factor (TVF). A distinguishing characteristic of TVF is that its calculation for a given thread (which is typically one of the threads of a multithreaded application) does not depend on its code alone, but also on the codes of the threads that share resources and ...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is i...
The vulnerability of multi-core processors is increasing due to tighter design margins and greater s...
Continuously reducing transistor sizes and aggressive low power operating modes employed by modern a...
With the scale down of transistor sizes and higher frequencies with low power modes in modern archit...
Modern architectures become more susceptible to transient errors with the scale down of circuits. Th...
Abstract—Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft erro...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Analyzing multi-threaded programs is quite challenging, but is necessary to obtain good multicore pe...
Abstract—The vulnerability of multi-core processors is increas-ing due to tighter design margins and...
© 2016 ACM. Relentless technology scaling has made transistors more vulnerable to soft, or transient...
Multicores have become the platform of choice across all market segments. Cost-eective protection ag...
In this dissertation we address the overhead reduction of fault tolerance (FT) techniques. Due to te...
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded proc...
With the scaling of technology, transient errors caused by external particle strikes have become a c...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is i...
The vulnerability of multi-core processors is increasing due to tighter design margins and greater s...
Continuously reducing transistor sizes and aggressive low power operating modes employed by modern a...
With the scale down of transistor sizes and higher frequencies with low power modes in modern archit...
Modern architectures become more susceptible to transient errors with the scale down of circuits. Th...
Abstract—Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft erro...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Analyzing multi-threaded programs is quite challenging, but is necessary to obtain good multicore pe...
Abstract—The vulnerability of multi-core processors is increas-ing due to tighter design margins and...
© 2016 ACM. Relentless technology scaling has made transistors more vulnerable to soft, or transient...
Multicores have become the platform of choice across all market segments. Cost-eective protection ag...
In this dissertation we address the overhead reduction of fault tolerance (FT) techniques. Due to te...
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded proc...
With the scaling of technology, transient errors caused by external particle strikes have become a c...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is i...
The vulnerability of multi-core processors is increasing due to tighter design margins and greater s...