Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, multicore machines are dominating the architectural spectrum in various application domains. These two trends require a fresh look at resiliency of multithreaded applications against transient errors from a software perspective. In this paper, we propose and evaluate a new metric called the Thread Vulnerability Factor (TVF). A distinguishing characteristic of TVF is that its calculation for a given thread (which is typically one of the threads of a multithreaded application) does not depend on its code alone, but also on the codes of the threads that share data with that threa...
International audience—Estimating the potential performance of parallel applications on the yet-to-b...
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Tech...
Soft error reliability has become a first-order design criterion for modern microprocessors. Archite...
Continuously reducing transistor sizes and aggressive low power operating modes employed by modern a...
With the scale down of transistor sizes and higher frequencies with low power modes in modern archit...
Modern architectures become more susceptible to transient errors with the scale down of circuits. Th...
Abstract—Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft erro...
Multicores have become the platform of choice across all market segments. Cost-eective protection ag...
Abstract—The vulnerability of multi-core processors is increas-ing due to tighter design margins and...
Analyzing multi-threaded programs is quite challenging, but is necessary to obtain good multicore pe...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is i...
While multicore processors improve overall chip throughput and hardware utilization, resource sharin...
Soft errors (also called transient errors, or single event upsets) are one of the vital errors that ...
In this dissertation we address the overhead reduction of fault tolerance (FT) techniques. Due to te...
International audience—Estimating the potential performance of parallel applications on the yet-to-b...
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Tech...
Soft error reliability has become a first-order design criterion for modern microprocessors. Archite...
Continuously reducing transistor sizes and aggressive low power operating modes employed by modern a...
With the scale down of transistor sizes and higher frequencies with low power modes in modern archit...
Modern architectures become more susceptible to transient errors with the scale down of circuits. Th...
Abstract—Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft erro...
Multicores have become the platform of choice across all market segments. Cost-eective protection ag...
Abstract—The vulnerability of multi-core processors is increas-ing due to tighter design margins and...
Analyzing multi-threaded programs is quite challenging, but is necessary to obtain good multicore pe...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is i...
While multicore processors improve overall chip throughput and hardware utilization, resource sharin...
Soft errors (also called transient errors, or single event upsets) are one of the vital errors that ...
In this dissertation we address the overhead reduction of fault tolerance (FT) techniques. Due to te...
International audience—Estimating the potential performance of parallel applications on the yet-to-b...
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Tech...
Soft error reliability has become a first-order design criterion for modern microprocessors. Archite...