Low power ASIC design, a comparative study

Includes bibliographical references (page 148)In the earlier generations the main focus was on the timings and area constraints. Power consumption was considered significant when there was a drastic increase of device densities from 130nm on. As technology advanced from 130nm to 90nm and below there was a significant increase in leakage current due to lesser threshold voltage. High power consumption will cause different problems such as increasing the cost of the product, reducing the reliability, reducing the battery life and many others. Therefore EDA tools were designed to maximize the speed while minimizing area. The main objective of this project is to successfully complete a comparative study of an ASIC design flow using 90 nm SYNOPSYS Design Compiler (DC) to generate the net list of the physical design and then use SYNOPSYS IC Compiler to perform the placement and optimization followed by clock tree synthesis, routing and lastly chip design. This project gives an overview of different types of ASIC, front end and back end design using SYNOPSYS Design Compiler and IC compiler flow. In this project FIFO design flow as is considered as an example will be done through the entire flow two times. Firstly, without applying any power techniques optimization through the front end as well as in the back end and secondly, by applying the low power techniques that can be implemented within the SYNOPSYS license that we have in school in front end as well as in back end also. First synthesis is done in front end using SYNOPSYS Design Compiler and net list is generated. Then the physical implementation of the design is done using SYNOPSYS IC Compiler. Power optimization using RTL level optimization and setting up power constraints is mainly considered