Low power USB protocol analyzer

Rapid changes in system on chip (SOC) power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. As the technology sizes of semiconductor devices continue to decrease, the effect of nanometer technologies on interconnects, such as power dissipation, become more significant. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distribution. Therefore, design for efficient power consumption is becoming a major design consideration. The objective of this project is to successfully complete a low power ASIC design flow using 90 nm technology libraries (ARM and SYNOPSYS). This project serves as a fundamental starting point and provides an overview of types of ASIC, standard design flow( Front and Back end), Synopsys Design Compiler and IC compiler flow, power related trade-offs, various low power design techniques and there effects on power consumption. Taking an USB protocol analyzer design as an example synthesis was done in front end using SYNOPSYS Design Compiler and physical implementation of the design was done using SYNOPSYS IC Compiler