Low power ASIC design of a wideband CDMA combiner

This thesis is a study of low power ASIC design of a WCDMA combiner. The focus is on low power design flow and different techniques used for low power ASIC's and how this can be used designing a WCDMA combiner. Different architectures and logic optimizations are evaluated by estimating the power consumption. In a mobile station the power consumption is a very important issue. With low power the size of the battery can be reduced or the usage time can be increased. Low power should be considered throughout the whole design cycle and not at a single location. Therefore, it is important to look at what can be done to reduce the power consumption and to avoid increasing power usage. Architecture selection and voltage scaling was explored to reduce power consumption in the thesis. This was done by writing VHDL for the different architectures and following the design flow for low power design. The power consumption was estimated and optimized with EDA tools. During the evaluation of the architectures, it was found that the resource-shared architectures had significant higher power consumption than the non-shared structures. This resulted in the selection of a non-shared architecture.Validerat; 20101217 (root