Implementation of complete ASIC design using low power methodology

Includes bibliographical references (pages 51)In today???s technological advancements in VLSI industry, the limits of ASICs/FPGA chips in terms of area, power and speed are constantly shrinking. The end user requirements are also influencing these limits and pushing them to a new level on top of all these technological advancements. The effects of nanometer technologies on congestion, signal integrity, crosstalk etc. are becoming more significant as the technology sizes of semiconductor devices continue to decrease. All of these factors are affecting and forcing various technological methodologies throughout the design flow to constantly fight and keep updating the EDA tools to cop-up with these issues. \ud Thus, there is always a need of constant learning and exposure to new advanced EDA tools like Synopsys Design Compiler, IC Compiler, PrimeTime, TetraMax etc. The aim of this project is to successfully complete the ASIC design flow with low power techniques, using the advance industry level tools. This project provides a solid base and practical hands-on experience of these advanced tools. It also provides an overview of types of ASICs, detailed ASIC standard design flow and Synopsys IC compiler flow. Along with this, the analysis of various design factors affecting the performance of the final chip such as power, area and timing is also performed.\ud In this project, a RISC CHIP from Synopsys will be used to perform ASIC design flow and low power methodology