An ASIC design and test methodology for an undergraduate design and fabrication project

During the 1990\u27s the main focus of chip design methodologies was on the timings and area constraints. Power consumption was considered significant only after a drastic increase of device densities from 130nm on as well as dramatic increases in sub threshold leakage. As technology advanced from 130nm to 90nm and below there was a significant increase in leakage current due to lower threshold voltage and the influence of the deep submicron effects. High power consumption causes different problems such as increasing the cost of the product, reducing the reliability, reducing the battery life among others. Therefore EDA tools were designed to maximize the speed while minimizing area and only recently focused on improving power. The main objective of this thesis is to complete a study of an ASIC (Application Specific Integrated Circuit) design and test flow to establish a full design methodology for an undergraduate class chip design and fabrication project from Verilog RTL to GDS2 for fabrication. The tools include Synopsys Design Compiler to generate a netlist of the physical design and Synopsys IC Compiler to perform the placement and optimization followed by clock tree synthesis, routing and lastly corechecking. The core is then inserted and connected with the chip pad frame using Synopsys Custom Designer. The final chip GDS generated will be sent to Mosis for fabrication. The Verification of the final chip design will be done using Cadence Virtuoso. This project gives an overview of different steps in the development of an ASIC, front end and back end design using Synopsys Design Compiler and IC compiler flow. In this thesis a simple 8 bit counter is considered as an example. This Thesis will provide the students with familiarity with the current industry standard tools from vendors like Synopsys and Cadence and the students will be well versed with a comprehensive ASIC design flow. The final design will be sent to Mosis for fabrication and the student teams will have working silicon in their hands with five packaged chip per project the demonstration of which will be beneficial when interviewing for a job in the chip industry