Low power implementation of SIA system controller

Funded by Northrop Grumman Company, the goal of this joint effort research project lead by Dr. Roosta is to redesign their legacy SiAc controller based on low power ASIC design methodology. The initial step is to replace the digital controller in an obsolete ACTEL FPGA to a digital ASIC. The ultimate low power solution is to implement the entire SiAc system including all the analog peripherals onto a mixed mode ASIC, a true System-on-Chip approach. One of the critical factors in today's SoC design is power consumption. The main focus was on timing and area in the earlier generations of IC design technologies. Power consumption was not that significant factor. However, power consumption was considered significant with the dramatic increase of device densities (from 130nm on) and clock frequencies in CMOS devices. As technology shrunk to 90nm and below there was a significant increase in leakage current due to less supply voltage as well as lower transistor threshold voltage which also increased power consumption. In today's world, total power consumption is a challenge for many applications, such as handheld devices, medical implantable devices, etc. Meeting the power budget is one of the most important design goals for today's SoC development. The objective of the project is to produce a low power physical design and tape out through MOSIS for fabrication. This report presents a detailed description of full front end to back end design flow of the SiAc ASIC, and serves the purpose of validating the entire design flow under CSUN's CAD system, covering a great number of tools from Synopsys and Cadence. And this chip represents a milestone for the ECE department, as it is the first ever truly fabricated ASIC in CSUN history