Specification of hazards, stalls, interrupts, and exceptions in EXPRESSION

Recent efforts in language-driven Design Space Exploration (DSE) use Architectural Description Languages (ADL) to capture the processor-memory architecture, generate automatically a software toolkit (including compiler, simulator, assembler) for that architecture, and provide feedback to the designer on the quality of the architecture. While some of these approaches capture the simple cases of hazards and interrupts in ADL, to our knowledge no previous approach has an explicit way of describing hazards and multiple exceptions for a wide variety of processors and memory architectures. In this report, we present a clean and uniform way of specifying hazards and exceptions in EXPRESSION which supports exploration and validation of programmable embedded systems. We present the study of interrupts and exceptions for Power PC, MIPS R10K, TI C6x and Intel IA-64 architectures