ADL++: object-oriented specification of complicated instruction sets and microarchitectures

This chapter focuses on the architecture description language (ADL)++, which allows automatic synthesis of cycle-accurate simulators, assemblers, and disassemblers from a specification written in the language. Its compiler is also implemented as part of the flexible architecture simulation toolset (FAST). The ADL++ language supports an execution model that is suitable for expressing a broad class of processor architectures. This execution model supports specification of the microarchitecture including pipelines, control, and the memory hierarchy including instruction and data caches, the assembly language syntax, and the binary representation. Instead of modeling hardware components, ADL++ explicitly models the instruction flow through some placeholders called pipeline stages, which make up the microarchitecture. This flow is tightly coupled with a clock built into the language, and the programmer explicitly specifies when an instruction can move from one stage to the next. The challenges posed by complex instruction set architectures are described by presenting the unique properties of Intel\u27s IA-32 instruction set architecture, which includes variable length instructions, too many addressing modes and overlapping registers, as well as mixed arguments in the instruction set. ADL++ artifacts can be used to describe the behavior of synchronous pieces of hardware and can be used to create arrays of artifacts, which then can be used as the building blocks of a more complicated hardware structure