Memory subsystem description in EXPRESSION

Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations for programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. However, such a processor-memory co-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this report the mechanism for describing memory subsystems in EXPRESSION, an Architecture Description Language (ADL) for processor-memory systems. The memory subsystem for the retargetable simulator can be generated from the description automatically. We have demonstrated the technique by generating memory subsystems for C6x, R10K, Itanium and Power PC architectures. We present a set of experiments using our memory aware ADL Language to drive the exploration of the memory subsystem for the TIC6211 processor architecture, demonstrating a range of cost and performance attributes