Exploring Memory Hierarchy with ArchC

This paper presents the cache configuration exploration of a programmable system, in order to find the best match-ing between the architecture and a given application. Here, programmable systems composed by processor and mem-ories may be rapidly simulated making use of ArchC, an Architecture Description Language (ADL) based on Sys-temC. Initially designed to model processor architectures, ArchC was extended to support a more detailed descrip-tion of the memory subsystem, allowing the design space exploration of the whole programmable system. As an ex-ample, it is shown an image processing application, running on a SPARC-V8 processor-based architecture, which had its memory organization adjusted to minimize cache misses. 1