Using standard Floating-Point (FP) formats for computation leads to significant hardware overhead since these formats are over-designed for error-resilient workloads such as iterative algorithms. Hence, hardware FP Unit (FPU) architectures need run-time variable precision capabilities. In this work, we propose a new method and an FPU architecture that enable designers to dynamically tune FP computations’ precision automatically at run-time called Variable Precision in Time (VPT), leading to significant power consumption, execution time, and energy savings. In spite of its circuit area overhead, the proposed approach simplifies the integration of variable precision in existing software workloads at any level of the software stack (OS, RTOS, ...
We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and a...
Solution of lnitial Value Problems (IVPs) is an important application in scientific computing. Metho...
International audienceThis paper proposes an innovative Floating Point (FP) architecture for Variabl...
International audienceFloating-Point (FP) computation using standard IEEE formats has a significant ...
International audienceFull-precision Floating-Point Units (FPUs) can be a source of extensive hardwa...
Modern communication systems such as 5G need high computational accuracy and dynamic range. Floating...
Full-precision Floating-Point Units (FPUs) can be a source of extensive hardware overhead in general...
In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor...
With the ever-increasing energy-efficiency requirements for the computing platforms at the edge, pre...
The slowdown of Moore's law and the power wall necessitates a shift toward finely tunable precision ...
In recent years approximate computing has been extensively explored as a paradigm to design hardware...
International audienceVariable Precision (VP) Floating Point (FP) is a solution to compensate accumu...
Modern embedded systems are in charge of an increasing number of tasks that extensively...
Many algorithms feature an iterative loop that converges to the result of interest. The numerical op...
We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and a...
Solution of lnitial Value Problems (IVPs) is an important application in scientific computing. Metho...
International audienceThis paper proposes an innovative Floating Point (FP) architecture for Variabl...
International audienceFloating-Point (FP) computation using standard IEEE formats has a significant ...
International audienceFull-precision Floating-Point Units (FPUs) can be a source of extensive hardwa...
Modern communication systems such as 5G need high computational accuracy and dynamic range. Floating...
Full-precision Floating-Point Units (FPUs) can be a source of extensive hardware overhead in general...
In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor...
With the ever-increasing energy-efficiency requirements for the computing platforms at the edge, pre...
The slowdown of Moore's law and the power wall necessitates a shift toward finely tunable precision ...
In recent years approximate computing has been extensively explored as a paradigm to design hardware...
International audienceVariable Precision (VP) Floating Point (FP) is a solution to compensate accumu...
Modern embedded systems are in charge of an increasing number of tasks that extensively...
Many algorithms feature an iterative loop that converges to the result of interest. The numerical op...
We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and a...
Solution of lnitial Value Problems (IVPs) is an important application in scientific computing. Metho...
International audienceThis paper proposes an innovative Floating Point (FP) architecture for Variabl...