International audienceFloating-Point (FP) computation using standard IEEE formats has a significant hardware overhead. Moreover, these formats are over-designed for most real-world applications, especially iterative refinement algorithms. Hence there is a need for hardware FP Unit (FPU) architectures with run-time variable precision capabilities.In this work, we propose a FPU architecture that enables designers to dynamically tune FP computations’ precision at run-time, leading to significant power consumption, execution time, and energy savings. Despite its additional circuit area overhead, the proposed architecture simplifies the integration of variable precision in existing software workloads at any level of the software stack (OS,...