Dynamic Scaling of Floating-Point Datapath Precision for Power Optimization

Modern communication systems such as 5G need high computational accuracy and dynamic range. Floating-point arithmetic in hardware can meet the computational requirement but the major issue is that they are power hungry. However, the high dynamic range and accuracy offered by floating-point Datapaths might not always be needed. It is possible that for certain cases, lower precision is enough while for other cases a higher accuracy is required. Hence, a dynamically adjustable Datapath of an embedded processor is proposed whose precision can be adjusted according to the demand of algorithms at runtime to decrease the power consumption. The scaling can either be initiated from within a program or from an external power-manager. The thesis is done in two distinct phases. The first phase of the thesis provides an estimation of accuracy loss when mantissa bits in standard single precision floating point representation are precision limited. Deriving from the results of estimation, several precision levels are chosen for an in-house embedded processor and power consumptions were estimated. The estimation of accuracy loss is accompanied by bit-accurate modelling in C and statistical analysis of model data on MATLAB. Similarly, the implementation is done using various Synopsys tools: ASIP Designer, VCS, Verdi, Design Compiler, and Formality. The power estimation on implemented design shows that there can be upto 30% saving in power consumption if the algorithm can tolerate 1.5% accuracy loss. The results also reveal that this saving can be achieved with only 4% increase in area of the processor