International audienceResearch on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient implementations. In this work, we propose to address this issue by leveraging well-known techniques used in superscalar processors to perform runtime memory disambiguation. Our approach, implemented as a source-to-source transformation at the C level, demonstrates significant performance improvements for a moderate increase in area while retaining portability among HLS tools
A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integ...
Current High-Level Synthesis (HLS) tools perform excellently for the synthesis of computation kernel...
When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructio...
International audienceResearch on High-Level Synthesis has mainly focused on applications with stati...
Loop pipelining is widely adopted as a key optimization method in high-level synthesis (HLS). Howeve...
In high-level synthesis (HLS), loop pipelining allows multiple iterations of a loop to be executed c...
High-level synthesis (HLS) automatically transforms high-level programs in a language such as C/C++ ...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for ...
The omission of support for several software-defined constructs within High-Level Synthesis (HLS) ha...
Abstract—The capabilities of modern FPGAs permit the mapping of increasingly complex applications in...
A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integ...
Current High-Level Synthesis (HLS) tools perform excellently for the synthesis of computation kernel...
When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructio...
International audienceResearch on High-Level Synthesis has mainly focused on applications with stati...
Loop pipelining is widely adopted as a key optimization method in high-level synthesis (HLS). Howeve...
In high-level synthesis (HLS), loop pipelining allows multiple iterations of a loop to be executed c...
High-level synthesis (HLS) automatically transforms high-level programs in a language such as C/C++ ...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for ...
The omission of support for several software-defined constructs within High-Level Synthesis (HLS) ha...
Abstract—The capabilities of modern FPGAs permit the mapping of increasingly complex applications in...
A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integ...
Current High-Level Synthesis (HLS) tools perform excellently for the synthesis of computation kernel...
When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructio...