When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructions, aiming to obtain a schedule that requires as few clock cycles as possible. However, when synthesising multi-threaded C programs, reordering opportunities are limited by the presence ofatomicoperations(‘atomics’), the fundamental concurrency primitivesin C. Existing HLS tools analyse and schedule each thread inisolation. In this article, we argue that thread-local analysisis conservative, especially since HLS compilers have access to the entire program. Hence, we propose a global analysis that exploits information about memory accesses by all threads when scheduling each thread. Implemented in the Leg Up HLS tool, our analysis is sensitive...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
Pointer analysis computes the set of memory locations that each pointer access can point to during h...
Modern architectures implement relaxed memory models which may reorder memory operations or execute ...
When mapping C programs to hardware, high-level synthesis (HLS) tools seek to reorder instructions s...
Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion but via f...
High-level synthesis (HLS) automatically transforms high-level programs in a language such as C/C++ ...
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a descript...
Dynamically scheduled high-level synthesis (HLS) enables the use of load-store queues (LSQs) which c...
Hardware Synthesis of Weakly Consistency C Concurrency This webpage contains additional material fo...
This collection contains the companion material of "Concurrency-Aware Thread Scheduling for High-Lev...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
High-Level Synthesis (HLS) tools automatically transform a high-level specification of a circuit int...
Strictness analysis is crucial for the efficient implementation of the lazy functional languages. A ...
International audienceResearch on High-Level Synthesis has mainly focused on applications with stati...
We present an algorithmic method for the quantitative, performance-aware synthesis of concurrent pro...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
Pointer analysis computes the set of memory locations that each pointer access can point to during h...
Modern architectures implement relaxed memory models which may reorder memory operations or execute ...
When mapping C programs to hardware, high-level synthesis (HLS) tools seek to reorder instructions s...
Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion but via f...
High-level synthesis (HLS) automatically transforms high-level programs in a language such as C/C++ ...
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a descript...
Dynamically scheduled high-level synthesis (HLS) enables the use of load-store queues (LSQs) which c...
Hardware Synthesis of Weakly Consistency C Concurrency This webpage contains additional material fo...
This collection contains the companion material of "Concurrency-Aware Thread Scheduling for High-Lev...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
High-Level Synthesis (HLS) tools automatically transform a high-level specification of a circuit int...
Strictness analysis is crucial for the efficient implementation of the lazy functional languages. A ...
International audienceResearch on High-Level Synthesis has mainly focused on applications with stati...
We present an algorithmic method for the quantitative, performance-aware synthesis of concurrent pro...
A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patte...
Pointer analysis computes the set of memory locations that each pointer access can point to during h...
Modern architectures implement relaxed memory models which may reorder memory operations or execute ...