The omission of support for several software-defined constructs within High-Level Synthesis (HLS) have hindered it’s broad adoption. Dynamic memory allocation is one feature that is not within the traditional supported subset. This works expands the synthesizable subset of the C languages for HLS tools, by including dynamic memory allocation algorithms (i.e. malloc and free). We define a variety of high-level synthesis approaches to support malloc and free. We first provide a library of HLS-friendly allocation algorithms, libmem, which is studied for performance and area impacts. We also define a framework to improve the performance and area of dynamic memory allocation mechanisms in HLS applications. Our framework employs a variety of dyna...
Abstract—The capabilities of modern FPGAs permit the mapping of increasingly complex applications in...
MOODS (Multiple Objective Optimisation in Data and control path Synthesis) is a behavioural synthesi...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
The omission of support for several software-defined constructs within High-Level Synthesis (HLS) ha...
Behavioural synthesis is the process whereby the description of a system behaviour is automatically ...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
VHDL is capable of describing the dynamic allocation of memory resources at ?run-time?. This paper d...
Memory-intensive implementations often require access to an external, off-chip memory which can subs...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Abstract—The capabilities of modern FPGAs permit the mapping of increasingly complex applications in...
MOODS (Multiple Objective Optimisation in Data and control path Synthesis) is a behavioural synthesi...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
The omission of support for several software-defined constructs within High-Level Synthesis (HLS) ha...
Behavioural synthesis is the process whereby the description of a system behaviour is automatically ...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
VHDL is capable of describing the dynamic allocation of memory resources at ?run-time?. This paper d...
Memory-intensive implementations often require access to an external, off-chip memory which can subs...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction Level (I...
Abstract—The capabilities of modern FPGAs permit the mapping of increasingly complex applications in...
MOODS (Multiple Objective Optimisation in Data and control path Synthesis) is a behavioural synthesi...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...